The concept of phase locking was invented in the 1930s and swiftly found wide use in electronics and communications. While the basic phase-locked loop has remained nearly the same since then, its implementation in different technologies and for different applications continues to challenge designers. A phase-locked loop serves the task of clock generation for a microprocessor as well as for frequency synthesizers for cell-phones.
Typically, a phase-locked loop is a non-linear analog device that uses a negative feedback loop to make the phase difference between an Input signal and an output signal smaller, preferably, approximately equal to zero. The phase difference between both signals becomes smaller and smaller, which also makes the frequency of both signals equal.
FIG. 1 depicts block diagrams of (a) a single-ended (signal-to-ground) and (b) differential phase-locked loop of the prior art. The phase locked-loop comprises three components: a phase detector, a low pass filter, and a voltage-controlled oscillator. In the single-ended version of FIG. 1a, an input voltage of a given frequency, VIN, is feed to one input of phase detector 101 on terminal 108-1 relative to ground potential. The output voltage of phase detector 101, VPD, feeds low-pass filter 102 on terminal 108-3. The output of low-pass filter 102, VLPF, feeds voltage-controlled oscillator 103. The output of voltage controlled oscillator 103, VVCO, is fed back to a second input terminal 108-2 of phase detector 101.
Phase detector 104, low-pass filter 105, and voltage-controlled oscillator 106 comprise a differential voltage phase-locked loop alternative to FIG. 1a. The main difference between FIG. 1b and 1a is that all signals are differential: input voltage VIN feeds phase detector 104 on terminals 107-1 and 107-2. The second set of differential Input terminals of phase detector 104, terminals 107-3 and 107-4, have the output signal of the voltage-controlled oscillator, VVCO impressed upon them. The output voltage of phase detector 104, VPD is fed to the input terminals 107-5 and 107-6 of low pass filter 105. Finally the output voltage of low-pass filter 105, VLPF is fed differentially to voltage controlled oscillator 106.
In the phase-locked loop of FIG. 1, the edges of VVCO are “skewed” by φ seconds with respect to VIN. Assuming that the VCO has a single control input, we note that to vary the phase, we must vary the frequency of the voltage-controlled oscillator. The output phase of the voltage-controlled oscillator can be stepped up or stepped down by momentarily changing the frequency of the voltage-controlled oscillator to “accumulate phase” faster until VVCO and VIN are aligned again.
Thus, there must be a means of comparing the two phases, i.e., a phase detector, is used to determine when the voltage-controlled oscillator and the reference signals are aligned. The task of aligning the output phase of the voltage-controlled oscillator with the phase of the reference is called “phase locking.”
What makes the signals smaller and smaller is the interaction of the phase detector and the voltage-controlled oscillator. It may seem that only these two components are needed. However, the control voltage of the voltage-controlled oscillator must remain quiet in the steady state. The phase detector output, VPD, typically contains both a DC component (desirable) and high-frequency components (undesirable), so that a low pass filter is interposed between the phase detector and the voltage-controlled oscillator.
Let us now analyze the response of a phase-locked loop in locked condition to a small phase or frequency transient at the input. FIG. 2 depicts timing diagrams of the phase-locked loop of FIG. 1a to a step change of phase. Initially the phase-locked loop is in the locked condition. Assume the input waveform of FIG. 2a and the output waveform of FIG. 2c can be expressed asVIN(t)=VA cosω1tVOUT(t)=VB cos(ω1t+φ0),Where higher harmonics are neglected and φ0 is the static phase error. When the input experiences a phase step of φ1 at t=t1 as in FIG. 2b. Since the output of the low pass filter does not change instantaneously, the voltage-controlled oscillator continues to oscillate at ω1. The growing phase difference between the input and the output then creates wide pulses at the output of the phase detector, as in FIG. 2d, forcing VLPF of FIG. 2e to rise gradually. As a result, the voltage-controlled oscillator frequency begins to change as shown in FIG. 2f in an attempt to minimize the phase error. Note that the loop is not locked during the transient because the phase error varies with time. If the loop is to return to lock, ωOUT of FIG. 2f must eventually go back to ω1, requiring that VLPF and hence φOUT -φIN also return to their original values. Consequently, as shown in FIG. 2, φOUT gradually “catches up” with φIN.
The phase detector can come in both digital and analog flavors. FIG. 3 depicts the logic diagram of a single-ended, digital implementation of phase detector 101 of the prior art. In FIG. 3a, the phase detector is simply an exclusive-or gate. FIG. 3b depicts two digital signals impressed on the inputs of the exclusive-or gate. The two signals are out of phase with each other by a difference of φ seconds. This results in an output waveform of the exclusive-or gate that is itself a pulse train. The width of the pulses is proportional to the difference in phase.
FIG. 4 depicts a schematic diagram of a differential analog version of the most common implementation of a phase detector in the prior art, known as a Gilbert Multiplier cell. Assuming all the transistors in FIG. 4 are biased in the saturation region and obey the ideal square-law equation and that devices are sized and matched so that the transconductance parameters satisfy the equation gm3=gm4=gm5=gm6=gma, and gm1=gm2=gmb. Defining the output currents Io1=−(I3+I5) and Io2=−(I4+I6), it can shown that if R1=R2, then differential output voltage VPD=R1(Io2−I01) orVPD=R1×VIN×VVCO×√{square root over (2gma×gmb)}The Gilbert Multiplier cell multiplies the two input waveforms in the time domain. So for sinusoidal inputsVPD(t)=sin(ωt)×sin(ωt+φ)Where    ω is the frequency in radians per second    t is time in seconds    φ is the phase difference between the two waveforms in radians.                               The  output  of  the  Gilbert  cell  is  therefore:                =                ⁢                  0.5          ⁢                      (                                          cos                ⁡                                  (                                                            ω                      ⁢                                                                                           ⁢                      t                                        -                                          ω                      ⁢                                                                                           ⁢                      t                                        -                    ϕ                                    )                                            -                                                                      ⁢                  cos          ⁡                      (                                          ω                ⁢                                                                   ⁢                t                            +                              ω                ⁢                                                                   ⁢                t                            +              φ                        )                                                  =                ⁢                  0.5          ⁢                      (                                          cos                ⁡                                  (                  ϕ                  )                                            -                              cos                ⁡                                  (                                                            2                      ⁢                                                                                           ⁢                      ω                      ⁢                                                                                           ⁢                      t                                        +                    ϕ                                    )                                                                        and when filtered by the low pass filter of a phase-locked loop produces a signal, VPD=0.5*cos(φ), a quantity directly proportional to the phase difference.